1. Field of Invention
This invention relates to semiconductor processing technology, and more particularly to the use of conventional processing technology to form very shallow junctions.
2. Relevant Background
In conventional deep submicron MOSFET, and other silicon devices, expansion of the drain potential into the channel region can result in short-channel effects. Regarding MOSFET devices, an ideal MOSFET has a junction depth of zero, and as a result has the least severe short-channel behavior. Thus, a conventional deep sub-micron transistor exhibits close to ideal performance characteristics when the source/drain (S/D) junctions are very shallow.
Very shallow junctions (&lt;500 .ANG.) with low leakage characteristics are very difficult to achieve with conventional semiconductor processing methods. More complex semiconductor processing methods, such as pre-amorphizing implants, sub-gate sidewall spacers or elevated S/D's are required to obtain adequately shallow junctions.
As semiconductor devices continue to reduce in scale, there are pressures to make junctions more shallow. Deep junctions result in an increase in the undesired short channel effects. Also, the overlap of S/D's onto the gate increases as the junction becomes deeper because of lateral diffusion. Large overlaps result in large overlap capacitance, which is a key parasitic characteristic that inhibits the intrinsic speed of MOS devices.
As devices scale from one generation to the next, large overlaps can be problematic. In general, large overlaps imply small effective lengths (L.sub.eff 's) for a fixed gate length. When L.sub.eff 's are small, channel concentration must increase to avoid pre-mature punch-through and to mitigate the drain induced barrier lowering (DIBL) effect. As channel concentrations increase, several deleterious effects can occur. These can include that channel mobilities degrade and reduce transistor gain; junction capacitance increases and reduces switching speed; junction breakdown decreases; body effect increases; and the temperature coefficient of threshold voltage increases. All of these factors improve as L.sub.eff increases, and the channel concentration decreases for a fixed physical gate length.
L.sub.eff can increase as the junctions become more shallow because of the reduced lateral diffusion, which is directly dependent on the depth of the junction. Thus, shallow junctions are highly desirable for deep sub-micron MOS devices. Similar arguments can be made for the desirability of shallow emitters and bases for bipolar devices.
With respect to reliability considerations, the low channel concentrations which accrue from shallow functions also act to reduce gate-induced drain leakage (GIDL) and the maximum electrical field (E.sub.max) at the drain. Reduced E.sub.max improves channel hot carrier (CHC) degradation immunity.
Present art using ion implantation even with pre-amorphizing implants, implant masking layers, and out-diffusion from dielectrics, metals and silicides are not readily capable of producing high concentration shallow P-N junctions. Pre-amorphizing implants eliminate ion channelling and reduce straggle but do not eliminate transient enhanced diffusion and long implant tails. Out-diffusion methods do not produce sufficiently high dopant concentrations, or are non-uniform, which produce leaky junctions.
Much attention has been paid to efforts aimed at finding feasible methods of manufacturing very shallow junctions, and to addressing the attendant problems and limitations associated therewith. It has been found that boron (B), BF.sub.2, phosphorous (P) and arsenic (As) cannot be driven from TiSi.sub.2 to form an adequate shallow junction. Thickness (x-ness) non-uniformity and thinning near the gate makes "drive-out" not feasible. For direct implantation into Si, implant damage (except for B) cannot be effectively annealed out at less than approximately 900.degree. C. Therefore, one must implant into silicide, which has inherent limitations on concentration. The result indicated that post-junction silicidation may not be able to be performed below the 0.5 .mu.m technology node.
It has also been found that one can recrystallize he amorphous region by performing solid phase epitaxy (SPE) at 550.degree. C. for 30 minutes, but a higher temperature is needed for fluorine (F)-implanted samples because F inhibits SPE. F inhibits SPE because it binds to crystal defects retarding SPE and B activation. It has been found that the junction thickness, x.sub.j, is approximately 0.11.mu. for a 1.35 KeV B implant, and 6 KeV BF2 when activated by rapid thermal annealing at 1050.degree. C. for 10 seconds. X.sub.j is approximately 0.075.mu. when used with a 27 KeV germanium (Ge) pre-amorphized substrate. Complete activation has been observed at 27 KeV Ge for rapid thermal annealing at temperatures as low as 600.degree. C. The temperature for defect removal is always higher than the temperature for activation.
In addition, it has been found that out-diffusion from CoSi.sub.2 with rapid thermal annealing for 10 seconds at 800.degree. C. produces an 8 nm x.sub.j for N.sup.+ and 23 nm x.sub.j for P.sup.+ junctions at 900.degree. C., with the junction being conformal to the Si/silicide interface. A 500.degree. C. anneal reduces leakage for all energies. For P.sup.+ -N junctions, lower energies need higher annealing temperatures. The F from BF.sub.2 acts to passivate any defects. For N.sup.+ -P junctions, 15 KeV has 10 times the leakage due to agglomeration of silicide, which acts to spike the junction. Low energy As was found to be more difficult to anneal because As diffusion is almost totally through grain boundaries and high concentrations are not achievable because of limited source concentrations. Furthermore, there is no F passivation, and any agglomeration has a greater effect on As.
Activation energy (E.sub.a) for leakage current on P.sup.+ /N junctions produced from CoSi.sub.2 out-diffusion is approximately 0.64 ev with a rapid thermal anneal at 600.degree. C. for 10 seconds in comparison to 1.0 ev with a rapid thermal anneal at 800.degree. C. for 10 seconds. This means that one has to anneal shallow junctions in Si at a minimum of 800.degree. C. in order to avoid leaky junctions.
The above describes the shallowest junctions attainable by the present state-of-the-art and some of the associated problems and limitations. There is missing in the art a method, using conventional processing methods, of producing very shallow junctions having desirable performance characteristics.